发明名称 FAULT PROCESSING SYSTEM
摘要 PURPOSE:To prevent a system from shutting off when a memory error is fixedly generated during the execution of a restart processing program on a singlet central processing system such as an exchange. CONSTITUTION:A memory error measurement counter 5, an OR circuit 6 inputting the OR output between a power-on reset signal and a multimemory error signal to a flip-flop 3, and an OR circuit 7 to be inputted to a restart control part 2 are provided on a fault processing part, and the memory error measurement counter 5 is counter up while using the memory error generation signal to be detected every time a memory error is generated as a clock. By a multimemory error signal to be outputted when the constant number of times of memory errors are generated, turning on a restart register and starting a start control part 2 are notified. By receiving this multimemory error signal, the start control part 2 recognizes that the power on bit is turned on, thereby executing the restart procedure at the time of turning on power supply.
申请公布号 JPH053575(A) 申请公布日期 1993.01.08
申请号 JP19910152081 申请日期 1991.06.25
申请人 FUJITSU LTD 发明人 FUJIZONO KENJI;IGI YOZO
分类号 G06F11/14;H04M3/22;H04Q3/545;H04Q3/58 主分类号 G06F11/14
代理机构 代理人
主权项
地址