发明名称 |
CIRCUIT FOR TRANSFERRING SIGNAL |
摘要 |
<p>PURPOSE:To excessively reduce wiring delay by permitting a MOS transistor for reducing input capacity to be serial capacity as against the gate capacity of an input MOS transistor when a selecting signal indicates nonselection. CONSTITUTION:The P-type MOS transistor MP1 and the two N-type MOS transistors MN1 and MN2 are connected in serial and a common clock line 100 is connected with the gate electrode of the transistor MN1. A block selection line SBi is connected with the gate electrode of the transistor MP1 and the transistor MN2 and a block output line Oi is connected with a connecting point between the drain electrodes of the transistor MP1 and the transistor MN1. The transistor MN2 constitutes serial capacity as against capacity between a gate and channel in the transistor MN1 as the input MOS transistor so as to reduce input capacity at the time of nonselection.</p> |
申请公布号 |
JPH052879(A) |
申请公布日期 |
1993.01.08 |
申请号 |
JP19910068342 |
申请日期 |
1991.04.01 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
YAMADA TOSHIRO |
分类号 |
G06F1/10;G11C11/401;G11C11/407 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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