| 摘要 |
<p>A semiconductor storing device is provided with a memory cell array (8) in connection with a data bus via a first selection circuit (6), a second selection circuit (7) responding to first control signals ( phi 0, phi x), a third selection circuit (8) responding to second control signals ( phi 1 - phi 8), a row address buffer (17) responding to the activation of a row address strobe signal, an address fetch circuit (21) which commands the fetch of a column address every predetermined number of toggled CAS signals, a column address buffer (19) responding to a third control signal fed from the address fetch circuit (21), a nibble decoder (38) for generating the first and second control signals, and a gate control circuit (39). During the period of activating row address strobe signal, after a column address is fetched, the next column address of the memory cell to be accessed is prefetched. <IMAGE></p> |
