VERFAHREN ZUM BILDEN VON BITSTELLENLEITUNGEN AUF EINEM HALBLEITER-WAFER
摘要
A DRAM fabrication process is disclosed for constructing a reduced resistance digit-line. The digit-line is so constructed as to maintain low resistance as it crosses the gaps between word-lines. By bridging gaps having a dimension less than or falling below a calculated critical gap spacing, and following the contours of gaps having a dimension greater or falling above that critical gap dimension, the digit-line resistance can be minimized.
申请公布号
DE4221511(A1)
申请公布日期
1993.01.07
申请号
DE19924221511
申请日期
1992.07.01
申请人
MICRON TECHNOLOGY, INC., BOISE, ID., US
发明人
RHODES, HOWARD E.;FAZAN, PIERRE C.;CHAN, HIANG C.;DENNISON, CHARLES H.;LIU, YAUH-CHING, BOISE, ID., US