发明名称 MULTIPROCESSOR ARRAY
摘要 <p>A multiprocessor computer system wherein a base processor is coupled in asynchronous O-ring fashion to an associated input/output adapter, with the processor and I/O adapter each including associated private cache memory through which they are both connected with a common shared MP bus via a single connector channel.</p>
申请公布号 WO1993000639(A1) 申请公布日期 1993.01.07
申请号 US1992005079 申请日期 1992.06.19
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