发明名称 Computer system with data transfer input control - has logic circuit connected between CPU and peripheral stages to control inputs and to avoid error conditions being generated
摘要 An interface connection circuit (1X) is located between a CPU (2A) and a peripheral circuit (1B) within the circuit is an input identification stage (3X) that has a NOR gate (11) and a buffer formed with inverters (3A) on the output connecting with the peripheral. A further buffer (16) is provided on one of the NOR gate inputs. The buffer receives an input from an "N" channel transistors switch (12). The other input of the NOR gate is provided by the I/O stage (2). The connecting operation occurs when the main switch (18) is actuated and the transistor stage (12) is operated for a specific period to control access. ADVANTAGE - Provides stable control of input lines in computer system.
申请公布号 DE4221023(A1) 申请公布日期 1993.01.07
申请号 DE19924221023 申请日期 1992.06.26
申请人 MITSUBISHI DENKI K.K., TOKIO/TOKYO, JP 发明人 INOUE, NAOKI, ITAMI, HYOGO, JP
分类号 G06F15/78;G06F1/24;G06F13/40 主分类号 G06F15/78
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