发明名称 Trench isolation method having a double polysilicon gate formed on mesas
摘要 A method of forming isolation trenches and mesa areas in a semiconductor substrate and of forming FETs in the mesa areas is disclosed. The method includes providing a first oxide layer, a first undoped polysilicon layer, and an etch stop layer on a silicon substrate. Isolation trenches and mesa areas are then defined by etching the substrate. A second oxide layer is provided to fill the isolation trenches, and is subsequently etched to remove second layer oxide above the mesa areas, thus exposing the first polysilicon layer. The method further comprises providing a second, conductively doped polysilicon layer over the exposed first polysilicon layer, wherein the first polysilicon layer is autodoped by the second polysilicon layer in a subsequent step. The first and second layers of polysilicon are patterned and etched to define FET gates in the mesa areas, with the first oxide layer beneath the first polysilicon layer being utilized as gate oxide.
申请公布号 US5177028(A) 申请公布日期 1993.01.05
申请号 US19910782002 申请日期 1991.10.22
申请人 MICRON TECHNOLOGY, INC. 发明人 MANNING, MONTE
分类号 H01L21/76;H01L21/28;H01L21/762;H01L29/78 主分类号 H01L21/76
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