| 摘要 |
Multiprocessor controller, especially a multiprocessor central control unit of a telephone switching unit, having a bus system (B:CMY) to which there are connected the processors (CP, IOC), which have a separate local memory (LMY) or no separate local memory (LMY), and which is allocated alternately to different processors of the group (e.g. CP1, CPx, IOC0). The multiprocessor controller has a main memory (CMY), which is connected to the bus system (B:CMY) and to which the processors (CP, IOC) can alternately have access in accordance with the allocations of the bus system (B:CMY) via the bus system (B:CMY), and via which processors (CP, IOC) can communicate with one another if required. The main memory (CMY) comprises a plurality of memory banks (MB) each having its own memory control which controls its own memory bank (MB) independently of the memory control of the remaining memory banks (MB). Time frames having time slots or time channels are set up in accordance with the time-division multiplex principle on the bus or busses of the bus system (B:CMY). One or more of the time channels are respectively firmly allocated to each memory control. For the purpose of quasi-simultaneous access to the different memory banks (MB), time slots or time channels can be allocated in each case to a plurality of the processors (CP, IOC). <IMAGE> |
