PHASE-LOCKED LOOP

摘要

A phase regulating circuit which converts a slot clock signal at an input into a slot-free clock signal with a low jitter at an output, comprises a phase discriminator, two identical frequency dividers and a regulating and oscillator circuit. The regulating and oscillator circuit comprises a quartz crystal oscillator which supplies an auxiliary frequency, and an adding counter which generates a further signal with a further frequency. One control input of the adding counter is connected for this purpose to the output of the phase discriminator, while a second input of the adding counter is connected to the output of the quartz crystal oscillator. The auxiliary frequency and the further frequency are each connected to an input of an EXCLUSIVE OR gate by which they are added by regular polarity reversal. From this added frequency, a frequency divider obtains the frequency of the clock signal. A plurality of phase regulating circuits can operate using a common quartz crystal oscillator which is of particular interest for digital signal multiplex devices.