| 摘要 |
<p>A semiconductor memory device comprising a plurality of memory cells disposed in the form of a matrix with column switch circuits and an address transition detecting circuit. The column switch circuits are each provided for each of said bit line pairs with their one end connected to a corresponding bit line pair and their other end connected to a data line pair for changing the potential difference between the lines of the data line pair according to the potential difference between the lines of the corresponding bit line pair. Each switch circuit is selectively activated according to a column address decoder signal and an output pulse signal of the address transition detecting circuit. <IMAGE></p> |
