| 摘要 |
The disclosed device is a programmable compensated digital delay circuit which has a design format suited for integrated circuitry utilizing complementary MOS technology. In the device, a signal-to-be-delayed is provided to the time delay cells which, are selectively interconnectable, for forming one or more delay configurations. In each delay cell, selectable capacitive elements are arrayed in a weighted manner and a memory programmably selects the capacitive elements by switching differently rated capacitive elements into and out of the circuit. Also, selectable current sources are arrayed in a weighted manner, and another memory programmably selects the current sources by switching differently rated current sources into and out of the circuit. The device further includes internal compensation, and, uses a ring oscillator for temperature and power supply compensation. The ring oscillator is formed from a plurality of time delay cells selected for interchangeability with the delay cells. Each ring oscillator has selected capacitive elements and current sources identical to the corresponding delay line. The output of the delay is connected to the input of the ring oscillator and through an error voltage circuit produces an error-voltage signal to adjust a variable current to the time delay cells. A pulse-width distortion compensation device is provided to compensate the delay line for switching non-linearities. The pulse-width compensation portion of the device serially connects an even number of complementary delay elements so as to cancel transfer function deviations.
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