发明名称 |
Low-power clock/calendar architecture |
摘要 |
An integrated circuit timekeeper, which uses a hybrid hardware/software architecture, wherein the least significant bits are updated in hardware and the more significant bits are updated in software. This hybrid architecture provides improved power efficiency, layout efficiency, and flexibility in reconfiguration.
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申请公布号 |
US5175699(A) |
申请公布日期 |
1992.12.29 |
申请号 |
US19880264233 |
申请日期 |
1988.10.28 |
申请人 |
DALLAS SEMICONDUCTOR CORP. |
发明人 |
PODKOWA, WILLIAM J.;WILLIAMS, CLARK R. |
分类号 |
G04G3/00;G04G99/00 |
主分类号 |
G04G3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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