| 摘要 |
A master bias voltage regulator circuit (5) has an output node for supplying a temperature compensated reference voltage (VREF1) to an input node of at least one slave ECL bias regulator circuit (4). The temperature compensated reference voltage is also compensated for a temperature-related characteristic of at least one ECL load, such as an ECL gate (2), and is also compensated for a temperature-related characteristic of the at least one slave ECL bias regulator circuit. VREF1 is sourced from an emitter of an output transistor (5Q7) and the collector of the output transistor is coupled to the emitter of a matching transistor. This technique is shown to provide improvements, relative to the prior art, in output reference voltage stability over variations in power supply voltage, temperature and process variations, while also reducing power consumption.
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