| 摘要 |
A multi-level potential generating circuit that brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential. The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage. The initial momentary discharge of the sense node to the first potential allows a sense amplifier to behave like a conventional sense amplifier during initial sensing, thereby allowing a minimum digit/digit* sensing potential to approximate ground. Decreasing the second potential to a third potential at the initiation of the precharge cycle effects a decrease in the equilibrate potential of the digit lines, thereby increasing the "high logic window" as reflected in an increase in cell margin and a decrease in soft error rate (SER).
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