INPUT AND OUTPUT PROCESSOR USING DATA BUFFER RAM

摘要

The circuit transmits data and command to a main memory of system level rapidly by using a data buffer RAM to improve the usage efficiency of input/output bus. The circuit includes a central processing unit (1) for controlling the input/output processor, a RAM (2) for storing some data needed to run a program, an EPROM (3), a buffer RAM (4), connected between the input/output bus (I/O BUS) and the system bus (MAIN BUS), for storing data and commands, a real time clock (RTC;6) for generating reference clock for the system, and an interrupt requester (7) .