| 摘要 |
PURPOSE:To shorten the lock up time by preventing the reduction of the frequency of the signal outputted from a phase comparator even at the time of the reduction of the frequency of a signal outputted from a variable frequency divider provided in a feedback loop or shortening the time constant of a low pass filter. CONSTITUTION:A frequency multiplying circuit 6 which multiplies the frequency of the signal outputted from a variable frequency divider 5 is inserted between the variable frequency divider 5 and the phase comparator 2 which are provided in the feedback loop of a PLL circuit. The frequency of the signal outputted from a reference signal source 1 is varied in accordance with the degree of multiplication of the frequency multiplying circuit 6. The frequency of the signal outputted from the phase comparator 2 is prevented from being reduced even at the time of reducing the frequency of the signal outputted from the variable frequency divider 6, or the degree of multiplication of the frequency multiplying circuit 6 is increased and the frequency of the signal outputted from the phase comparator 2 is raised to shorten the time constant of the low pass filter. |
