发明名称 Bit string oriented computer architecture for image processing and communications protocol - uses chip with serial data paths or addressing bit fields of variable length, and transfers bits with time offset
摘要 The computer architecture provides for the transfer of individual bits between the functional units of the computer with a time offset, via internal serial transmission paths and bus systems. The functional units operate serially and with bit strings of variable length. The information transferred may include memory addresses to the main memory, instructions from the main memory to the controller, data words between the arithmetic unit and the main memory, control information to computer peripherals, or data words between processor registers and arithmetic logic units. Direct addressing of the main memory is executed on bit boundaries. USE/ADVANTAGE - Battery powered computers and communications terminals, e.g. facsimile machines, image encoders or compressors, computer monitor graphics controller, mains-fed terminals and network interfaces. Reduced interconnections.
申请公布号 DE4215506(A1) 申请公布日期 1992.12.24
申请号 DE19924215506 申请日期 1992.05.12
申请人 SCHULTHESS, PETER, PROF. DR., 7900 ULM, DE 发明人 SCHULTHESS, PETER, PROF. DR., 7900 ULM, DE
分类号 G06F9/38;G06F13/42;G06F15/78 主分类号 G06F9/38
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