发明名称 |
GEGOSSENES KUNSTSTOFF-CHIP-GEHAEUSE MIT STECKERMUSTER. |
摘要 |
An improved plastic molded chip carrier package for a semiconductor chip [1,40] has a plurality of I/O pins [20,60] arranged on a pin grid array. The pin grid array comprises at least two row of the I/O pins [20,60] disposed along the sides of the chip [1,40] in such a manner that the I/O pins [20,60] are staggered with respect to those in the other row. The staggered arrangement of the I/O pins [20,60] makes it easy to provide electrical interconnection between the I/O ports on the chip [1,40] and the corresponding I/O pins [20,60] without requiring an elaborate or crowded wiring or connection lines. This is particularly effective when an increased number of the I/O pins [20,60] are required to be included in the limited area of the chip carrier. |
申请公布号 |
DE3780764(T2) |
申请公布日期 |
1992.12.24 |
申请号 |
DE19873780764T |
申请日期 |
1987.11.09 |
申请人 |
MATSUSHITA ELECTRIC WORKS, LTD., KADOMA, OSAKA, JP |
发明人 |
HIRATA, ATSUOMI, IKOMA-GUN NARA, JP;NAKAMURA, YOSHIHIKO, NISHINOMIYA HYOGO, JP;MORII, KENSAKU, TAKATSUKI-SHI OSAKA, JP |
分类号 |
H01L23/055;H01L23/24;H01L23/498 |
主分类号 |
H01L23/055 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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