| 摘要 |
<p>PURPOSE:To eliminate read error of specific bit data in a prescribed frame format in a synchronous transmission network by discriminating whether the phase of a read clock is equal or opposite to that of a write clock to generate the read clock which rises in the center of reception data. CONSTITUTION:When reception data 1 is inputted to a buffer 10, a high-speed reception clock is converted to a write clock 2 having the same period as data 1 and a control clock 4 having a short pulse width by a converting circuit 20. A high-speed transmission clock is inputted to a converting circuit 30 together with a read clock 3 having the same period as the data 1 and an inverted read clock 3' to generate a control clock 5 having the same period as the clock 3 and a short pulse width and a control clock 6 existing within the pulse width of the clock 5. A discriminating part 40 generates first and second select signals in accordance with the presence or the absence of the clock 6 in clocks 4 and 5. A selector 50 selects the read clock 3 and the inverted read clock 3' in accordance with first and second select signals and gives them to a buffer 10.</p> |
