| 摘要 |
PURPOSE:To obtain an accurate delay time in a delay-time forming circuit by installing a capacitor formed by connecting each parasitic capacitance of first and second MOS transistors in parallel to a semiconductor device and forming the semiconductor device so that the electrostatic capacitance of the capacitor reaches an approximately fixed value when parasitic capacitance depending upon voltage difference changes. CONSTITUTION:P channel and N channel MOS transistors 13, 14 are formed onto a P-type substrate 11 as a pair while holding a field oxide film 12. Both gates G of the P channel and N channel transistors 13, 14 are connected in common by aluminum electrodes, each source S and srain D of both transistors are also connected mutually while the mutually bonded sources S and drains D of each transistor 13, 14 are bonded in common, and a pair of terminals 22, 23 of the capacitance element are formed while being extended from the connected nodes 20, 21 in common of each transistor. The voltage characteristics of the whole synthesized capacitance element are flattened approximately, thus reducing the voltage dependency of a capacitance value.
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