Vertical synchronization processing circuit.

摘要

A vertical synchronization processing circuit which comprises a counter for counting a clock signal synchronized with a horizontal sync. signal, a circuit for resetting the counter in response to a vertical synchronization signal within a predetermined limit prohibiting reset due to a non-standard signal, a memory for storing the data counted at the timing of reset, and a circuit for changing a predetermined limit prohibiting reset due to a non-standard signal according to the data from the memory. A vertical synchronization processing circuit which comprises a counter for counting a clock signal synchronized with a horizontal sync. signal, a first resetting circuit for resetting the counter in response to a vertical synchronization pulse within a predetermined limit prohibiting reset due to a non-standard signal, a circuit for discriminating an existence of a vertical synchronization interval, and a second resetting circuit for resetting the counter if the discriminating circuit detects the existence of the vertical synchronization interval when the counter counts a predetermined number of clock signals in case that there is not a vertical synchronization pulse within the predetermined limit. <IMAGE>