SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: To improve an yield by providing a control circuit which transmits complementary input/output data to complementary input/output lines when a redundant memory cell is substituted for the data state of a defective normal memory cell. CONSTITUTION: The input gates of redundant memory cells R1 and R2 are controlled. A circuit 10 which changes the data states of the cells R1 and R2 at need in addition to redundant enable signals REN1 and REN2 is provided. The data states of the cells C1 and C2 before substitution are known by using the address signal CAi of a column determining the data states of the normal memory cells C1 and C2 and the relation between the C1, and R1 and R2 is known from signals REN1 and REN2. Therefore, the outputs of AND gates 40 and 50 for the signals REN1 and REN2, and the inverse of CAi and CAi are used, and the states of data input/output states of reading and writing can be controlled by circuits RRDC80 and RRDC90 and RWDC100 and RWDC110 controlling data output and input can be adjusted. Consequently, the yield can be improved.