| 摘要 |
PURPOSE:To suppress jitter of an output clock by minimizing a deviation from a desired lock point even when a frequency difference is in existence. CONSTITUTION:An output of a reference clock oscillation section 101 is inputted to a variable frequency divider section 102 and its output is inputted to a frequency divider section 103. An output from a control area generating section 106, that is, an area to decide a phase control variable blocked by a predetermined phase difference is inputted to one input of a control area shift section 107 and an output of a frequency deviation detection section 108 is inputted to the other input. Furthermore, an output of the control area decision section 104 is inputted to a frequency division ratio setting section 105, in which a frequency division ratio equivalent to the phase control variable corresponding to the area decided by the control area decision section 104 is set and the variable frequency division section 102 adds or deletes the clock pulse by the increase/decrease and the phase of the output clock is subject to lead/lag control in a direction made coincident with the input clock(ICLK). |
