| 摘要 |
PURPOSE: To enable applications, especially for the phase control of lock signal at a synchronizer. CONSTITUTION: This time constant circuit is provided with plural number of transfer gates G0, G1...Gn composed of MOS transistors, while composing resistance elements of the drain-source paths. Since the capacity of this circuit is the structural capacity of MOS transistors, by selectively making the transfer gates (RE0, RE1...REn), time constants can be controlled. In order to keep the fixed value of capacity, auxiliary compensation circuits GC0, GC1...GCn are added to the respective transfer gates G0, G1...Gn. When these gates are made active, capacitors C0, C1...Cn at the same values as the capacitances of conducted gates are introduced. Furthermore, this time constant circuit is provided to a delay circuit which uses it. |
