| 摘要 |
PURPOSE:To attain both the drive of an output with a large load at a high speed and the operation of a logic circuit of a next stage at a high speed with out increasing an input capacity of the buffer. CONSTITUTION:Two logic circuits 1, 2 whose capability differs are connected in parallel, input levels of the two logic circuits 1, 2 are added in an opposite phase in the steady-state and when the input level changes, the outputs of the two logic circuits are added in phase to bring an output level in the steady-state in the vicinity of a logic threshold level VLTH of a logic circuit B of the next stage and the amplitude of the output signal is increased at a change in the input level. |
