| 摘要 |
PURPOSE:To reduce the chip area in the case of circuit integration with less number of elements. CONSTITUTION:An input clock signal is inputted to a PMOS 7 and NMOS 9, outputted from an output terminal B, and the input clock signal is inputted to PMOS 4 and an NMOS 3 via an inverter 30, outputted from an output terminal C, and a PMOS 8 and an NMOS 5 connecting the output terminals B,C to a power supply 20 in response to an output of other output terminal mutually to form the two phase clock generating circuit with PMOS 4,5,7,8 and the NMOS 3,9 in addition to the PMOS 1 and the NMOS 2 constituting the inverter 30. |
