发明名称 |
Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication |
摘要 |
An integrated circuit is provided wherein bipolar, CMOS and DMOS devices are merged together on one chip with fabrication taking place from a CMOS point of view rather than from a bipolar point of view as in the prior art and p-type epitaxial silicon is used as opposed to n-type epitaxial silicon in the prior art. The integrated circuit uses a P+ substrate upon which a P-epitaxial layer is formed. N+ buried regions isolate the DMOS, PMOS and NPN bipolar devices from the P-epitaxial layer. Each of the devices is formed in a N-well with a first level of polysilicon gate layer providing both the gate and masking for the backgate diffusion of the DMOS device and a sidewall oxide later formed on the first level gate layer to control the diffusion of the source and drain regions of the DMOS device to control channel length. A second level of polysilicon layer provides the gate structures for the CMOS devices as well as one plate of a capacitor. The second level of polysilicon acts as a mask for the source and drain region implants of the CMOS devices. A sidewall oxide later formed on the second polysilicon level further controls the channel lengths of the CMOS structures. A third level of polysilicon provides the second capacitor plate for the capacitor. The DMOS device is isolated from the remaining circuitry by the p-type epitaxial layer and the peripheral portion of the DMOS device is terminated by a PN junction.
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申请公布号 |
US5171699(A) |
申请公布日期 |
1992.12.15 |
申请号 |
US19900592108 |
申请日期 |
1990.10.03 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
HUTTER, LOUIS N.;ERDELJAC, JOHN P. |
分类号 |
H01L21/336;H01L21/761;H01L21/8238;H01L21/8249;H01L27/06;H01L27/088;H01L29/78 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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