| 摘要 |
In a semiconductor memory cell of a DRAM comprising a stacked cell capacitor constructed upon word and bit lines, the stacked cell capacitor is not directly connected to a transistor to the device isolator area is provided. Through this wiring, the diffusion layer of the transistor is connected to the stacked cell capacitor. Also, a bit line is constructed on the active region to cross the connection point between the transistor, local wiring and gate electrode.
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