| 摘要 |
<p>PURPOSE:To make operations into a pipeline and to perform access to a memory in a shortest cycle by temporarily latching read data and parity by a latch circuit, completing the operation of a memory bus and afterwards executing a parity check. CONSTITUTION:When a request signal comes from a system bus in the case of a memory read cycle, a memory controller 1 generates a control signal required for access and according to this control signal, the data and the parity are read out of the memory. These data and parity are temporarily latched by a latch circuit 7 at timing for a host to accept the data, and the access cycle of the host side is finished. On the other hand, the next cycle is started at the system bus from this point of time and at a parity check/judgement circuit 5, however, the truth of the preceding access is judged. Then, the result is latched and outputted to the outside according to a parity error latch timing signal to be outputted from the memory controller 1 at the next timing.</p> |
