| 摘要 |
PURPOSE:To quickly and surely discriminate synchronization state and out of synchronism of a multi-frame even when a bit number of a register is considerably reduced. CONSTITUTION:A specific bit (1st, 9th,..., 49th bit) of a 64-bit shift register 1 shifting an input signal by one bit each is compared with a horizontal synchronization pattern at a horizontal synchronization detector 2, which outputs a horizontal synchronizing signal and at least a 57th bit data of the signal is inputted to a 16-bit shift register 3h, which is shifted at an interval of one frame, and a specific bit (5th, 7th,..., 15th bit) is compared with a vertical synchronization pattern at a vertical synchronization detector 4 after one multi- frame is stored, a vertical synchronizing signal is outputted and a synchronization control circuit 5 discriminates the synchronization state based on both the synchronizing signals and a data clock. |
