| 摘要 |
This invention employs a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division. A dividend is stored in a register B and a divisor, in a register C. A selector 6 selects register B when the result of subtraction by an adder/subtracter 1 is positive or zero, and selects register A at other times. Both adder/subtracter 1 and a shifter 2 receive the signal from the selector 6 in the same way, and execute the subtraction processing and the shift processing, respectively. The results of these processings are stored in the registers B and A', respectively. The division time can be shortened because the adder/subtracter 1 and the shifter 2 can be actuated simultaneously. |
