| 摘要 |
<p>PURPOSE:To enable subjective evaluation by simulating the characteristic of an ATM (asynchronous transfer mode) communication system to handle various speed data and images, etc., at real time at high speed. CONSTITUTION:The prescribed bit of a cell having a fixed length is deleted by a means (first data memory 2, detection and addition control circuit 5 and detection and addition circuit 6) to delete and add the bit by replacing it with fixed data, and stored in a second data memory 7. A means (memory write control circuit 4, cell delay time control circuit 9, cell output time memory 10, cell output time monitor circuit 11 and memory read control circuit 12) is provided to delay the stored cell for prescribed time. Further, a means (bit error control circuit 13 and bit error addition circuit 14) is provided to add bit error by inverting the prescribed bit of the cell read out of the second data memory 7.</p> |
