| 摘要 |
<p>A clock run-in sequence of equally spaced similar input pulses is sampled at a much higher frequency and the samples converted to single bits. The resulting sequence of bits is fed into a shift register (7) the stages of which are connected to logic means (8) which produces indications when the bits stored in the register represent a centrally located input pulse or space between input pulses. The clock pulses driving the sampler are fed to frequency divider (18) which produces the local clock signal. The local clock signal is synchronised with the clock run-in sequence by deriving the average phase of the frequency divider at a number of indications and adjusting the phase of the divider accordingly.</p> |
