| 摘要 |
PURPOSE:To easily multiplex other data onto an idle data area of a start/stop bit by providing a specific sampling circuit and a circuit adding valid/invalid bit to a data for each prescribed unit so as to improve the transmission efficiency of packet communication. CONSTITUTION:With a signal inputted from an asynchronous communication terminal equipment 11 to an interface circuit 3, the signal is converted into an electric level suitable for a next stage sampling circuit 12A. When the converted signal is inputted to the circuit 12A, the signal is sampled at a speed being a several number of multiple of the transmission speed and a prescribed signal format is decoded. That is, a start bit or a stop bit being a redundant bit is eliminated and valid data is sent to an FIFO memory 15 as one unit. The FIFO memory 15 is controlled by an asynchronous timing generating circuit 13 for each unit and write operation is implemented. |
