| 摘要 |
<p>Bus cycle control means for a computer having a primary bus for receiving signals from a processing unit (CPU) and a secondary bus (MCA Bus) for accessing other components comprising indicating means for artifically indicating to the processing unit (CPU) that a cycle initiated on the secondary bus (MCA Bus) is complete before it has actually been completed whereby the processing unit (CPU) is able to carry out other functions on the primary bus whilst the cycle on the secondary bus (MCA Bus) is being completed. <IMAGE></p> |
