Space compression technique for pseudo-exhaustive self-testing of digital electronic circuits.

摘要

Compaction of the response signals produced by separate sets of sub-circuits within a digital circuit under test is accomplished by first analyzing each response signal produced by a corresponding set of sub-circuits (by way of a logic analyzer (16,18) to determine if the response signal has a particular pattern. A pattern bit is then set in accordance with the response signal which has the particular pattern. The pattern bits are then compacted by a set of daisy-chained time compactors (20), each compactor serving to exclusively OR the pattern bit from a corresponding logic analyzer (16,18) with a compacted bit generated previously by an upstream compactor. <IMAGE>