发明名称 Method of forming a multilayer wiring structure on a semiconductor device.
摘要 <p>In a process for manufacturing a semiconductor device having a multi-layer wiring structure, a silicon oxide film is deposited on the surface of second level wiring conductors formed on a power supply layer for electroplating, and then, the deposited silicon oxide film is etched back so that the silicon oxide film remains only on the side surfaces of the second level wiring conductors. Thereafter, the power supply layer is removed by the sputter etching, and the silicon oxide film is etch-removed together with the metal deposit adhered to the surface of the silicon oxide film at the time of the sputter etching. Accordingly, the short-circuiting of adjacent second level wiring conductors which would be caused because of peeling-off of the metal deposit is prevented.</p>
申请公布号 EP0517551(A2) 申请公布日期 1992.12.09
申请号 EP19920305240 申请日期 1992.06.08
申请人 NEC CORPORATION 发明人 INABA, TAKASHI
分类号 H01L21/302;H01L21/3065;H01L21/3213;H01L21/768;H01L23/532 主分类号 H01L21/302
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