| 摘要 |
PURPOSE:To proceed the parallel operation of an instruction in a pipe line without being interrupted as much as possible by providing a stop means and stopping the delay of the execution of the instruction by means of a delay means. CONSTITUTION:When a micro instruction C1 is an instruction for writing data into the register R of a register part 12, and a micro instruction C2 is an instruction for reading data from the same register R by one pipe line, a score boarding part 15 supervising a number designation signal (a) and an R/W designation signal (b) discriminates access to the same register R and an execution delay signal (d) is outputted to an execution control part 10 from the score boarding part 15. The execution of one pipe line of the micro instruction C2 is delayed by the prescribed number of clocks after the micro instruction C1 is executed. Then, a score boarding stop part 16 discriminates that the micro instruction C2 requires plural clocks, and the output of the execution delay signal (d) is stopped after the prescribed number of the clocks. Then, the instruction C2 is executed. |
