Phase and frequency-locked loop circuit having expanded pull-in range and reduced lock-in time

摘要

A phase/frequency-locked loop (P/FLL) circuit for generating output signals synchronized with input signals in frequency and phase. The circuit includes a phase comparator which responds to the input signals and to the output signals to develop therefrom phase comparison signals in the form of positive or negative voltages corresponding to the phase differences between the input and output signals. A filtering circuit produces from the phase comparison signals a control signal for a voltage controlled oscillator (VCO) which produces in turn an oscillation signal having a frequency corresponding to the control signal. A phase controller responds to the control signal for the VCO as well as to the output oscillation signal thereof and produces the output signals in a form and wave shape which cause the control signal for the VCO to have a single voltage polarity. The P/FLL circuit of the invention reduces the time required to pull-in the frequency of the VCO and also expands the pull-in range.