| 摘要 |
PURPOSE:To attain error detection correction even in a data transmitter without increasing a bit rate by adding an error check correction code to a frame pulse signal. CONSTITUTION:A parallel signal PDi inputted to a parallel serial converter 102 of a transmission section is converted into a serial signal Do, the one is sent to a coding circuit 103, in which the signal is calculated according to the code rule and the result of calculation is fed to a check bit addition circuit 104. The check bit addition circuit 104 adds the result of calculation to a frame pulse signal representing a head of the serial signal Do and the resulting output Fo is outputted. On the other hand, the serial signal Di inputted to a receiver side is converted into a parallel signal PDo at a serial parallel converter 205 and calculated by a decoding circuit 203. A check bit demultiplexer circuit 202 receives a frame pulse signal Fi and separates the FP signal representing the head of the serial signal Di and the check bit. Then a comparator circuit 204 compares the result of calculation sent from a decoding circuit 203 with the check bit and outputs the result of comparison Eo. |
