Asynchronous timing circuit for a 2-coordinate memory

摘要

PCT No. PCT/EP88/01215 Sec. 371 Date Aug. 13, 1990 Sec. 102(e) Date Aug. 13, 1990 PCT Filed Dec. 24, 1988 PCT Pub. No. WO90/07777 PCT Pub. Date Jul. 12, 1990.An asynchronous timing or control circuit (TIM) for a RAM memory applies a row selection (ROWD) signal to one end (WIO/WIN) of a selected memory row (WORDO/WORDN) and a corresponding control signal (WOO/WON) is collected at the other end (WOO/WON) of this row through a common NOR gate (04) with an input for each row. Since this control signal reflects the propagation time of a signal through the row, it is used to control the precharging (PRECHB) of the memory columns prior to any subsequent read or write operation, the latter using the same row selection signal.