| 摘要 |
<p>PURPOSE:To realize high speed read operation of memory cell data without increase of circuit scale and device forming area in a semiconductor storage device in which a readout data is output by comparing a memory cell potential with the reference potential like EPROM or mask ROM using a floating gate type MOSFET as a memory cell. CONSTITUTION:A dummy cell 81 for changing a charging speed is connected in parallel with dummy cells 12l to 12m connected to a dummy bit line DBL and this dummy cell 81 is controlled for ON and OFF status by a control circuit 80. Thereby, a charging speed for the dummy bit line DBL by a second load circuit 50 is lowered, in the initial condition of charging, than the reference potential Vrcf generated by a first load circuit 30 and a potential difference between the bit lines BL1 to BLn and dummy bit line DBL is used for detection of readout data of '1' and '0' in the initial stage of the charging by a data detection circuit 70.</p> |
