| 摘要 |
<p>PURPOSE:To prevent erroneous write in and erroneous erasure of nonselection memory transistors. CONSTITUTION:A memory cell array 800 is configured by memory array configuration groups arranged in a matrix from and each memory array configuration group is selected by plural memory transistors QM1,1 to QM2,6 and first selection transistors QS1,1 to QS2,6 which are connected to the memory transistors in parallel. Each memory array configuration group is connected to bit lines through second selection transistors QC1 to QC4 and the second selection transistors are selected by selection lines C1 to C2. During a write in and a read out period, a memory transistor which is the same memory array configuration group is selected by first word lines X1 to X6 and the first selection transistors which make pairs with the selected memory transistors are turned off by second word lines Z1 to Z6. Since the first selection tracsistors, which are paried with the other nonselection memory transistors, are turned on, these first selection transistors act as trnasfer gates and prevent erroneous write in and erroneous erasure of nonselection memory transistors.</p> |
