| 摘要 |
PURPOSE:To reduce testing man-hours by providing a testing circuit which simultaneously compares stored data read out into the corresponding bit lines from plural memory cells, connected to the selected word lines of each memory array, per bit line and per word line unit. CONSTITUTION:X address coders XD0 and XD1 decode internal address signals and selectively make the corresponding word lines of memory arrays ARY0 or ARY1 a high level selected condition. As a result, arrays ARY0 or ARY1 are selectively activated and the n+1 memory cells, which are connected to the selected word lines, output minute read out signals corresponding to the respective holding data against corresponding complementary bit lines B0* to Bn*. And the arrays ARY0 and ARY1 are selectively activated according to internal signals when a dynamic type RAM becomes a normal write in or a read out mode and simultaneously activated by the dynamic type RAM. |
