| 摘要 |
PURPOSE:To prevent the fluctuation of a phase from being accumulated even when a reference signal is switched at the clock preparing circuit which prepares mutually various reference signals while inputting the two kinds of clock signals and outputs any one of the reference signals corresponding to an external signal. CONSTITUTION:A counter circuit 2 is provided as a first frequency dividing means to prepare a first reference signal 20 frequency dividing a first clock signal 100 into N (N is a positive integer and a counter circuit 7 is provided as a second frequency dividing means to prepare a second reference signal 70 frequency dividing a second clock signal 200 into the N. In the counter circuit 2, a reference signal 21 is prepared with the almost same pulse width as one cycle of the clock signal 200 while defining the change point of the first reference signal 20 as a center, and clock selectors 5 and 9 and a rise detection circuit 8 are provided as switching means to switch the first reference signal 20 to the second reference signal 70 at the change timing of the second clock signal 200 while this reference signal 21 is existent. |
