| 摘要 |
<p>PURPOSE:To reduce the mis-detection ratio and to establish resynchronization state in a short time by comparing a current state level signal outputted from a detection means with a state level signal of one preceding block period outputted from a latch means. CONSTITUTION:A state comparator 5 outputs a count start pulse S8 when an output of a detector 3 reaches a synchronization level, a counter 7 outputs a synchronization detection pulse S10 and a latch circuit 9 latches a state level signal outputted from the detector 3. Moreover, an address and a data signal S12 detected and protected by an address protection circuit 11 are outputted via a control circuit 13. Then a state level signal S7 latched at an interval of one block and a state level signal S6 detected at an interval of reproduction clocks are inputted to the comparator 5, in which they are compared and synchronization/nonsynchronization state is discriminated. Thus, the mis-detection rate is reduced and re-synchronization state is obtained in a short time.</p> |
