PHASE SYNCHRONIZING CLOCK EXTRACTING CIRCUIT

摘要

PURPOSE:To stably extract a phase synchronizing clock from a reception burst signal by separating clock selection and clock determination and using the clock determination result to extract the phase synchronizing clock. CONSTITUTION:A multiphase clock generating circuit 2 generates plural M- sequence clock pulse trains different in phase. A change point detecting circuit 1 detects the change point of the rise or the fall of the reception burst signal. A clock selecting circuit 3 selects pulse trains, which include pulses whose timing practically coincides with the change point detection timing of the change point detecting circuit 1, from M-sequence clock pulse trains, and a clock determining circuit 4 determines the pulse train to be actually selected based on the selection result. A determination result holding circuit 5 holds the output of the clock determining circuit 4 till new output. A selector circuit 6 selects and outputs one of M-sequence clock pulse trains in accordance with the output of the determination result holding circuit 5.