发明名称 RETRIAL SYSTEM FOR INFORMATION PROCESSOR
摘要 PURPOSE:To facilitate control at the time of retrial in an information processor. CONSTITUTION:A processing circuit 101 previously executes the same processing for a processing circuit 120 by a prescribed clock cycle. When a detection circuit 104 in the processing circuit 101 detects a mechanical error or a logically illegal event, it is informed to the processing circuit 120 through a mutual control signal line 110. Thus, the state of an internal resource 113 in the processing circuit 120 is transferred to an internal resource 103 in the processing circuit 101 through an internal resource information transfer line 111. When a detection circuit 114 in the processing circuit 120 detects the mechanical error or the logically illegal event, the state of an internal resource 103 in the processor 101 is transferred to the internal resource 113 in the processing circuit 120. Thus, a processing for saving the internal resource becomes unnecessary and therefore control at the time of retrial becomes facile.
申请公布号 JPH04347736(A) 申请公布日期 1992.12.02
申请号 JP19910149730 申请日期 1991.05.24
申请人 NEC CORP 发明人 OKI HIDETAKA
分类号 G06F11/14;G06F11/18;G06F15/16;G06F15/177 主分类号 G06F11/14
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