发明名称 Semiconductor integrated circuit device having wells biased with different voltage levels.
摘要 <p>A semiconductor integrated circuit device is fabricated on a lightly doped n-type silicon substrate (11), and p-type wells (13/ 14) are formed in the silicon substrate, wherein a heavily doped n-type channel stopper (21) is formed in a surface portion (20) between the p-type wells for restricting a parasitic channel between the p-type wells, and the surface portion is doped at a predetermined impurity concentration larger than a remaining portion of the silicon substrate and smaller than the channel stopper so that a p-n junction hardly takes place between the inverted surface portion and the channel stopper. &lt;IMAGE&gt;</p>
申请公布号 EP0515833(A1) 申请公布日期 1992.12.02
申请号 EP19920106884 申请日期 1992.04.22
申请人 NEC CORPORATION 发明人 NAKASHIBA, YASUTAKA
分类号 H01L27/08;H01L21/339;H01L21/76;H01L27/02;H01L27/148;H01L29/06;H01L29/762 主分类号 H01L27/08
代理机构 代理人
主权项
地址