Fabrication method in vertical transistor integration.

摘要

In some circuitry, field effect transistors are produced by employing polycrystalline conductive regions including the channel and connections to the source and drain. Conventional methods for producing such transistors involve depositing a thin polycrystalline channel region, patterning this region overlying the patterned region with an insulator, producing openings in the insulator for contacts to source and drain, and depositing a thick polycrystalline contact region. Processing complexity is, however, substantially reduced by first forming interconnect areas source region and drain regions (24); then opening a region (42) for the channel; and finally depositing a layer (23) to form the channel. Thus, at least three processing steps are eliminated and vertical dimensions are reduced.